Program

Wednesday, 03/Apr/2024

8:00 - 9:00 Registration

9:00 - 9:30 Opening Session

9:30 - 10:30 Keynote 1: Chris Myers

10:30 - 11:00 Coffee Break

11:00 - 12:30 Session 1: Emerging Technologies

12:30 - 14:00 Lunch

14:00 - 15:30 Session 2: Dependability Analysis and Assessment

15:30 - 16:00 Coffee Break

16:00 - 17:15 Embedded Tutorial

17:15 - 17:45 Poster Pitches

17:45 - 18: 30 Poster Session

18:30 - 19:30 Session 3: Analog Circuits

20:00 Welcome Reception

Thursday, 04/Apr/2024

9:00 - 10:00 Keynote 2: Matthias Pflanz

10:00 - 11:00 Session 4: Reverse Engineering and Countermeasures

11:00 - 11:30 Coffee Break

11:30 - 12:30 Session 5: Cryptography

12:30 - 14:00 Lunch

14:00 - 15:00 Session 6: Hardware Optimization

15:00 - 19:00 Social event

19:00 Gala Dinner

Friday, 05/Apr/2024

8:30 - 9:30 Keynote 3: Tom Waayers

9:30 - 11:00 Session 7: Novel Hardware Design Approaches

11:00 - 11:30 Coffee Break

11:30 - 13:00 Session 8: Fault-Tolerant Platforms

13:00 - 13:30 Best Paper Award & Closing

13:30 - 14:30 Lunch

Detailed Programme

Wednesday, 03/Apr/2024

8:00 – 9:00 Registration
9:00 – 9:30 Opening Session
9:30 – 10:30 Keynote 1
Moderator: Chris Myers (University of Colorado Boulder) – Chair: Andreas Steininger
Design of Asynchronous Genetic Circuits
10:30 – 11:00 Coffee Break
11:00 – 12:30 Session 1: Emerging Technologies (Session chair: Lukas Sekanina)

  • Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators
    Klhufek Jan, Safar Miroslav, Mrazek Vojtech, Vasicek Zdenek, Sekanina Lukas
  • Performance and Error Tolerance of Stochastic Computing-based Digital Filter Design
    Sengupta Roshwin, Polian Ilia, Hayes John P.
  • Early detection of permanent faults in DNNs through the application of tensor-related metrics
    Turco Vittorio, Ruospo Annachiara, Sanchez Ernesto, Sonza Reorda Matteo

12:30 – 14:00 Lunch
14:00 – 15:30 Session 2: Dependability Analysis and Assessment (Session chair: Jan Schmidt)

  • SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators
    Taheri Mahdi, Pappalardo Salvatore, Jenihhin Maksim, Bosio Alberto, Daneshtalab Masoud, Deveautour Bastien, Raik Jaan
  • An Autonomous Clock Frequency Supervision Circuit
    Scharwitzl Clemens, Steininger Andreas
  • A New Reliability Analysis of RISC-V Soft Processor for Safety-Critical Systems
    Cora Giorgio, De Sio Corrado, Rizzieri Daniele, Azimi Sarah, Sterpone Luca

15:30 – 16:00 Coffee Break

16:00 – 17:15 Embedded Tutorial (Session  chair: Petr Fiser)

  • On-Chip Cross-Layer Infrastructure to Leverage System Reliability for Aero-Space Applications
    Fabian Luis Vargas (IHP – Leibniz Institute for High Performance Microelectronics, Germany)

17:15 – 17:45 Poster Pitches

17:45 – 18: 30 Poster Session

  • Choose your Path: Control of Ring Oscillators EMFI Susceptibility through FPGA P&R Constraints
    Sami EL AMRAOUI, Régis LEVEUGLE, Paolo MAISTRI
  • Evaluating the Reliability of Integer Multipliers With Respect to Permanent Faults
    Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Serag Eldin Habib
  • Adaptive Input Normalization for Quantized Neural Networks
    Jan Schmidt, Petr Fišer, Miroslav Skrbek
  • Interface protection against transient faults
    Ján Mach, Lukáš Kohútka, Pavel Čičák
  • An Efficient High-level Synthesis Implementation of the MUSIC DoA Algorithm for FPGA
    Sakari Lahti, Tuomas Aaltonen, Elizaveta Rastorgueva-Foi, Jukka Talvitie, Bo Tan, Timo D. Hämäläinen
  • A ML-based Approach for Finding the Product Definition Space of Microelectronic Power Switches
    Seyedbehnam Beladi, Linus Maurer, Jonas Stricker, Georg Pelz
  • Constant Voltage Maximum Power Point Tracking Method for Fully Integrated Solar-Powered Energy Harvester
    Adam Hudec, Robert Ondica, Richard Ravasz, Viera Stopjakova

18:30 – 19:30 Session 3: Analog Circuits (Session chair: Witold Pleskacz)

  • The Impact of Well-Edge Proximity Effect on PMOS Threshold Voltage in Various Submicron CMOS Technologies
    Grochowska Marika, Pleskacz Witold
  • A Low-Noise High-Voltage Rail-to-Rail Operational Amplifier with Gain Stabilization and Slew-Rate Enhancement (online)
    Pan Jie, Li Fanyang, Yuan Yidong, Zhao Tianting, Shen Hongwei, Wen Liguo, Hu Yi, Jin Jiazhen, Wu Shuwen

20:00 Welcome Reception

Thursday, 04/Apr/2024

9:00 – 10:00 Keynote 2
Moderator: Matthias Pflanz (IBM Research & Development, Boeblingen/ Germany)  – Chair: Mario Schölzel
Challenges for highly-reliable High-Performance Processor Development

10:00 – 11:00 Session 4: Reverse Engineering and Countermeasures (Session chair: Ilia Polian)

  • Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track
    Brunner Michaela, Lee Hye Hyun, Hepp Alexander, Baehr Johanna, Sigl, Georg
  • Fault-Simulation-Based Flip-Flop Classification for Reverse Engineering
    Mildner Michael, Brunner Michaela, Gruber Michael, Baehr Johanna, Sigl Georg

11:00 – 11:30 Coffee Break

11:30 – 12:30 Session 5: Cryptography (Session chair: Ilia Polian)

  • Optimised AES with RISC-V Vector Extensions
    Namazi Rizi Mahnaz, Zidaric Nusa, Mentens Nele, Batina Lejla
  • Xoodyak Under SCA Siege
    Amiri Eliasi Parisa, Batina Lejla, Mella Silvia, Picek Stjepan, Weissbart Léo

12:30 – 14:00 Lunch

14:00 – 15:00 Session 6: Hardware Optimization (Session chair: Florian Huemer)

  • PaGoRi:A Scalable Parallel Golomb-Rice Decoder
    VADDEBOINA Mounika, Kaja Endri, Yilmazer Alper, Ghosh Uttal, Ecker Wolfgang
  • Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences
    Zielasko Jan, Krauss Rune, Merten Marcel, Drechsler Rolf

15:00 – 19:00 Social event

  • 15:00 – Departure from the hotel

  • 15:15 – A walk around Kadzielnia Nature Reserve

  • 16:00 – Visiting the National Museum (main branch)
  • 19:00 – Gala dinner at the Oranżeria restaurant

Friday, 05/Apr/2024

8:30 – 9:30 Keynote 3
Moderator: Tom Waayers (NXP semiconductors) – Chair: Alberto Bosio
DfT for achieving 0 DPPB, are we there yet ?

9:30 – 11:00 Session 7: Novel Hardware Design Approaches (Session chair: Pawel Sitek)

  • ABACUS: ASIP-based Avro Schema-customizable Parser Acceleration on FPGAs
    Hahn Tobias, Schüll Daniel, Wildermann Stefan, Teich Jürgen
  • A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks
    Schmidt Jan, Fišer Petr, Skrbek Miroslav
  • QDI Binary Comparator Networks and their Application in Combinational Logic
    Huemer Florian

11:00 – 11:30 Coffee Break

11:30 – 13:00 Session 8: Fault-Tolerant Platforms (Session chair: Fabian Luis Vargas)

  • An Efficient Approach for STLs Development of Automotive SoCs Using Colored Petri Nets
    Villegas Castillo Ernesto Cristopher, Augusto da Silva Felipe, Glaß Michael
  • TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection
    K K Raghunandana, K R Yogesh Prasad, Reorda Matteo Sonza, Singh Virendra
  • On the Fault Tolerance of Self-Supervised Training in Convolutional Neural Networks
    Milazzo Rosario, De Marco Vincenzo, De Sio Corrado, Fosson Sophie, Morra Lia, Sterpone Luca

13:00 – 13:30 Best Paper Award & Closing

13:30 – 14:30 Lunch